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low power precision analog microcontroller arm cortex m3, with dual sigma - delta adcs preliminary technical data ADUCM360/aducm361 rev. pr r information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog dev ices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2012 analog devices, inc. all rights reserved. features analog input/output dual (24- bit) adcs (ADUCM360) single (24 - bit) adc (aducm361) single ended and fully differential inputs programmable adc output rate (4 hz to 4 khz) simultaneous 50hz/60hz rejection 50sps continuous conversion mode 16.67sps single conversion mode flexible input mux for input channel selection to both adcs primary and auxiliary (24 - bit) adc channel 6 differential or 11 single - ended input channels 4 internal channels for monitoring dac, temperature sensor, iovdd and avdd (adc1 only) programmable gain (1 to 128) selectable input range: 6.64 mv to 1.2 v rms noise: 4 3 nv @ 3.75 hz, 1 80 nv @ 50hz programmable sensor excitation current sources 10/50/100/150 /200/250/300/400/500/600/800ua and 1ma current source options on - chip precision voltage reference ( 4 ppm / c) single 12 - bit voltage output dac npn mode for 4 - 20ma loop applications microcontroller arm cortex? - m3 32 - bit processor serial wire download and debug internal watch crystal for wakeup timer 16 mhz oscillator with 8 - way programmable divider memory 128k bytes flash/ee memory, 8k bytes sram in - circuit debug/download via serial wire and uart power operates directly from a 3.0v battery supply range: 1. 8v to 3.6v (max) power consumption mcu active mode: core consumes 29 0a / mhz active mode: 1. 0 ma (all peripherals active), core operating at 500khz power down mode: 4a (wu timer active) on - chip peripherals uart, i2c and 2 x spi serial i/o 16- bit pwm cont roller 1 9 - pin multi - function gpio port 2 general purpose timers wake - up timer / watchdog timer multi - channel dma and interrupt controller package and temperature range 48 lead lfcsp (7mm x 7mm) package C 40c to 125c development tools low - cost quickstart? development system third - party compiler and emulator tool support multiple functional safety features for improved diagnostics applications industrial automation and process control intelligent, precision sensing systems 4 ma to 20 ma loop - powered smart sensor systems medical devices, patient monitoring
ADUCM360/aducm361 preliminary technical data rev. pr r page 2 of 21 untna da gra a i n 0 a i n 1 a i n 5 / i e x c a i n 1 0 d a c a i n 4 / i e x c a i n 1 1 / v b i a s 1 a i n 3 a i n 2 a i n 6 / i e x c a i n 7 / i e x c / v b i a s 0 / e x t _ r e f 2 i n + a i n 8 / e x t _ r e f 2 i n - a i n 9 a g n d i r e f a v d d 1 9 g e n e r a l p u r p o s e i / o p o r t s p o r o n - c h i p o s c ( 3 % ) 1 6 m h z g p i o p o r t s u a r t p o r t 2 x s p i p o r t s i 2 c p o r t a r m c o r t e x - m 3 m c u 1 6 m h z p r e c i s i o n r e f e r e n c e r e s e t x t a l 0 x t a l 1 v r e f + g n d _ s w m e m o r y 1 2 8 k b f l a s h 8 k b s r a m t i m e r 0 t i m e r 1 w a t c h d o g w a k e u p - t i m e r p w m . . 1 2 - b i t d a c v r e f - m u x s i n c 3 / 4 f i l t e r a m p . . . b u f o n - c h i p 1 . 8 v d i g i t a l l d o . . . v b i a s g e n . . . . . . o n - c h i p 1 . 8 v a n a l o g l d o d a c , t e m p , i o v d d / 4 a v d d / 4 d m a + i n t e r r u p t c o n t r o l l e r s e r i a l w i r e d e b u g + p r o g r a m m i n g & d e b u g b u f . . . . s e l e c t a b l e v r e f s o u r c e s v r e f s w c l k s w d i o d v d d _ r e g a v d d _ r e g i o v d d i o v d d 1 0 / 5 0 / 1 0 0 / 2 0 0 / 5 0 0 / 7 5 0 / 1 0 0 0 u a c u r r e n t s o u r c e s . b u f i n t _ r e f . . s i n c 2 f i l t e r . . . . . . ? ? m o d u l a t o r 2 4 - b i t ? ? a d c s i n c 3 / 4 f i l t e r . v r e f . s i n c 2 f i l t e r ? ? m o d u l a t o r 2 4 - b i t ? ? a d c . . a m p . . . . . . figure 1. ADUCM360 block diagram
preliminary technical data ADUCM360/aducm361 rev. pr r | page 3 of 21 table of contents features ............................................................................................... 1 fu nctional block diagram ............................................................... 2 general description .......................................................................... 4 specifications ..................................................................................... 5 ADUCM360/aducm361 microcontroller electrical specifications ................................................................................. 5 noise resolution of primary and auxiliary adcs ................ 10 i 2 c timing diagrams ................................................................. 12 spi timing diagrams ................................................................. 13 absolute max imum ratings .......................................................... 16 esd caution ................................................................................ 16 outline dimensions ........................................................................ 21
ADUCM360/aducm361 preliminary technical data rev. pr r page 4 of 21 general description the ADUCM360 is a fully integrated, sps, - it data acui - sition system incorporating dual, high performance multi - channel sigma - delta - analog - to - digital conerters adcs, 3- it arm cortex m3 mcu, and flash/ee memory on a single chip the part is designed f or direct interfacing to external precision sensors in oth wired and attery powered applications the aducm361 contains all the features of the a d ucm360 except the primary adc, adc 0 is not aailale only the auxiliary adc, adc1 is aailale the deice contains an on - chip 3 h oscillator and an internal 16mh high - freuency oscillator this cloc is routed through a programmale cloc diider from which the mcu core cloc operating freuency is generated the maximum core cloc speed is 16mh and this is not limited y operating oltage or temperature the microcontroller core is a low power cortex - m3 core from arm it is a 3 - it risc machine, offering up to 0 mips pea performance the cortex - m3 mcu incorporates a flexile 11 - channel dma controller supporting all wired spi, uart, i c communication peripherals 1 bytes of non - olatile flash/ee and bytes of sram are also integrated on - chip the analog su - system consists of dual adc s each connected to a flexile input mux both adcs can operat e in fully differential and single ended modes other on - chip adc features include dual programmale excitation current sources, urn - out current sources and a ias oltage generator of addreg/ 00m to set the common - mode oltage of an input channel a low - side internal ground switch is proided to allow powering down of a ridge etween conersions t he adcs contain two parallel filters a sinc3 or sinc in parallel with a sinc the sinc3 or sinc filter is for precision measurements the sinc fil ter is for fast measurements and for detection of step changes in the input signal the deice also contains a low noise, low drift internal and - gap reference or can e configured to accept up to external reference source s in ratiometric measurement configurations an option to uffer the external reference input s is also proided on - chip a single - channel uffered oltage output dac is also proided on chip the a d ucm360/ aducm361 also integrates a range of on - chip periphe rals which can e configured under microcontroller software control as reuired in the application these peripherals include uart, ic and dual spi serial i/o communication controllers, 1- pin gpio ports, general purpose timers, ae - up timer and system atchdog timer a 16- it pm with six output channels is also proided the ADUCM360 / aducm361 is specifically designed to operate in attery powered applications where low power operation is critical the microcontroller core can e configured in a norma l operating mode consuming 0 a/mh including flash/sram idd resulting in an oerall s ystem current consumption of 1 ma when all peripherals are actie the part can also e configured in a numer of low power operating modes under direct program contro l, including hiernate mode internal wae - up timer actie consuming only a in hiernate mode, peripherals such as external interrupts or the internal wae up timer can wae up the deice this allows the part to operate in an ultra - low power operating mode and still respond to asynchronous external or periodic eents on - chip factory firmware supports in - circuit serial download ia a serial wire interface - pin tag system and uart while non - intrusie emulation is also supported ia the serial wire interface these features are incorporated into a low - cost uicstart deelopment system supporting this precision analog microcontroller family the part operates from an external 1 to 36 oltage supply and is specified oer an industrial temperature range of - 0c to 1c
preliminary technical data ADUCM360/aducm361 rev. pr r | page 5 of 21 specifications ADUCM360/aducm361 microcontroller elec trical specification s avdd/iovdd = 1.8 v to 3.6v, internal 1.2v reference, f core = 16 mhz, all specifications t a = 40c to 125c , unless otherwise noted. table 1 . ADUCM360 / aducm361 specifications parameter test conditions/comments min typ max unit adc specifications conversion rate 1 chop off 4 4 000 hz chop on 4 1333 hz both primary & auxiliary channels no missing codes 1 chop off (f adc 500 hz ) 24 bits chop on (f adc 250 hz) 24 bits rms noise and data output rates see noise and resolution tables in the user guide integral nonlinearity 1 gain = 1 gain = 2, 4, 8 , 16, 32, 64, 128 15 2 5 ppm of fsr ppm of fsr offset error , 2 , 3 chop off, offset error is in the order of the noise for the pro - grammed gain and update rate following calibration 100/gain v offset error 1 , 2 , 3 chop on 1.0 v offset error drift vs. temperature 4 chop off 100/ gain nv/c chop on 10 nv/c offset error drift vs. time tbd nv/1000 hours full - scale error 1 , 5 , 6 , 7 0.5 /gain tbd m v gain drift vs. temperature 4 gain = 1 to 16, external reference 1 ppm/c gain = 32 to 128 external reference 3 gain error drift vs. time tbd ppm/1000 hours pga gain mismatch error 0.1 5 % power supply rejection 1 , 8 chop on, adc = 0.25 v ( gain = 4 ), ext. reference 85 db chop o ff , adc = 7.8 mv ( gain = 128), ext. reference 100 db chop off, adc = 1 v ( gain = 1), ext. reference 85 db absolute input voltage range unbuffered m ode gain=1 agnd a v dd v buffered mode gain =1 agnd+ 100mv avdd - 100mv v unbuffered mode : differential input voltage ranges 1 gain >=2 gain = 1 gain = 2 gain = 4 gain = 8 gain = 16 gain = 32 (avdd >=2.0v) (avdd <2.0v) gain = 64 (avdd >=2.0v) agnd avdd vref 500 250 125 62.5 26.56 18.75 13.28 mv mv mv mv mv mv mv mv mv
ADUCM360/aducm361 preliminary technical data rev. pr r page 6 of 21 arameter test onditionsomments in tp a unit (avdd <2.0v) gain = 128 (avdd >=2.0v) (avdd <2.0v) 9.375 6.64 4.6875 mv mv mv common mode voltage, vcm 1 vcm=(ain(+)+ain( - ))/2, gain= 2 to 128 input current will be higher when vcm <0.5v agnd v input current 1 , 9 gain = 1, buffered mode (excluding pins with v b ias) 1 na gain >1, buffered mode (excluding pins with v b ias) 2 na unbuffered mode. input current will vary with input voltage 500 na/v average input current drift buffered mode : ain0, ain1, ain2, ain3 ain4, ain5, ain6, ain7 ain8, ain9, ain10, ain11 5 16 9 pa/c pa/c pa/c unbuffered mode 250 pa/v/c common - mode rejection dc 1 on adc input adc g ain =1 70 100 adc g ain =2 to 128 80 db common - mode rejection 1 50 hz/60 hz 50 hz/60 hz 1 hz, 16.7 hz update rate, chop on 50 hz update rate, chop off adc g ain =1 9 7 db adc g ain = 2 to 128 9 0 db normal - mode rejection 1 50 hz/60 hz on adc input 50 hz/60 hz 1 hz, 16.6 hz f adc/ chop on, 50 hz f adc/ chop off 60 80 db temperature sensor after user calibration voltage output at 25c mcu in power down or standby mode before measurement 82.1 mv voltage tc 250 mv/c accuracy 6 c ground switch ron 12 ohms allowable current with 20k resistor off C direct short to ground 20 ma voltage reference adc precision reference internal v ref 1.2 v initial accuracy 1 measured at t a = 25c - 0.05 0.05 % reference temperature coefficient (tempco) 1 , 8 ?15 8 +15 ppm/c power supply rejection 1 100 db
preliminary technical data ADUCM360/aducm361 rev. pr r | page 7 of 21 parameter test conditions/comments min typ max unit external reference input range buffered mode unbuffered mode minimum differential voltage between vref+ and vref - pins is 400mv 0 0 avdd - 0.1 avdd v v input current buffered mode 15 na unbuffered mode 500 na/v normal mode rejection 80 common mode rejection 78 db reference detect levels 400 mv excitation current sources output current available from each current source C 10/50/200ua nominal 10 50 1000 a initial tolerance at 25c iout >= 50ua 5 % drift 1 using internal reference resistor 200 ppm/c using external 150 k? reference resistor between iref pin and agnd. resistor must have a drift spec of 5ppm/c 75 ppm/c initial current matching at 25c 1 matching between both current sources 0.5 % drift matching 1 50 ppm/c load regulation ( avdd ) 1 avdd = 3.3 v 0.2 %/v output compliance 1 10ua to 210ua iout agnd ? 30 mv avdd ? 0.85 v v iout >210ua agnd ? 30 mv avdd ? 1.1 v v dac channel specifications r l = 5 k?, c l = 100 pf voltage range internal reference 0 v ref v external reference 0 1.8 v dc specifications 10 resolution 12 bits relative accuracy 3 lsb differential nonlinearity guaranteed monotonic 0.5 1 lsb offset error 1.2 v internal reference 2 15 mv gain error npn mode resolution relative accuracy differential nonlinearity v ref range (reference = 1.2 v) 12 1.0 0.5 1 % bits lsb lsb offset error gain error output current range 1 0.008 0.35 0.75 23.6 ma ma ma dac ac characteristics voltage output settling time 10 s digital - to - analog glitch energy 1 lsb change at major carry (where maximum number of bits simultaneously change in the dac0dat register) 20 nv - sec
ADUCM360/aducm361 preliminary technical data rev. pr r page 8 of 21 arameter test onditionsomments in tp a unit power - on reset (por) por trip level refers to voltage at dvdd pin power - on level 1.6 v power - down level 1.6 v timeout from por 50 ms watchdog timer (wdt) timeout period 1 0.00003 8192 sec timeout step size t3con[3:2]=[10] 7.8125 ms flash/ee memory 1 endurance 11 20,000 cycles data retention 12 tj=85c 10 years digital inputs all digital inputs logic 1 input current (leakage current) v inh =vdd or v inh = 1.8v internal pull - up disabled reset , swclk, swdio 10 100 na a logic 0 input current (leakage current) v inl = 0v internal pull - up disabled reset , swclk, swdio 10 100 na a input capacitance 10 pf logic inputs vinl, input low voltage 0.2 x vdd v vinh, input high voltage 0.7 x vdd v logic outputs voh, output high voltage i source = 1ma vdd C 400mv v vol, output low voltage i sink = 1ma 0.4 v crystal oscillator 1 logic inputs, xtali only 13 input low voltage (vinl) 0.8 v input high voltage (vinh) 1.7 v xtali capacitance 6 pf xtalo capacitance 6 pf on - chip low power oscillator oscillator 32,768 khz accuracy ?20 +20 % on - chip high frequency oscillator oscillator 0.125 2 16 mhz accuracy to be confirmed across full temperature range of - 40 to +125c -1 1 % mcu clock rate eight programmable core clock selections within this range: 0.125 2 16 mhz using an external clock 0.032768 16 mhz mcu start - up time at power - on includes kernel power - on execution time 41 ms after reset event includes kernel power - on execution time 1.44 ms
preliminary technical data ADUCM360/aducm361 rev. pr r | page 9 of 21 parameter test conditions/comments min typ max unit from mcu power - down (mode 1, 2 and 3) fclk is the cortex - m3 core clock 3 - 5 x fclk from total - halt or hibernate (mode 4 or mode 5) mode 30.8 s power requirements power supply voltages vdd 1.8 3.6 v power consumption i dd (mcu active mode) 14, 15 mcu clock rate = 16 mhz, all peripherals on 5.5 ma mcu clock rate = 500 khz, both adcs on (input buffers off ) with pgas gain = 4, 1 x spi on, all timers on 1 ma i dd (mcu powered down) 1 full temperature range hibernate (mode 5) 4 10 a reduced temperature range ?40c to +85c 2 5 a i dd (primary adc) (total) 15 pga enabled C total, g>=32 320 a pga g=4/8/16 C pga only 130 a g=32/64/128 C pga only 180 input buffers 2 x input buffers is 70ua 70 a digital interface + modulator 70 a i dd (auxiliary adc ) input buffers off, g=4/8/16 only 200 a external reference input buffers 60ua each 120 a 1 these numbers are not production tested but are guaranteed by design and/or characterization data at production release. 2 tested at gain range = 4 after initial offset calibration. 3 measured with an internal short. a system zero - scale calibration removes this error. 4 a recalibration at any temperature removes the se errors. 5 these numbers do not include internal reference temperature drift. 6 factory calibrated at gain = 1. 7 system calibration at a specific gain range removes the error at this gain range. 8 measured using the box method . 9 input current measured with one adc measuring a channel. if both adcs measure the same input channel, then the input current will increase C approximately double 10 reference dac linearity is calculated using a reduced code range of 0x0ab to 0xf30 . 11 endurance is qualified to 20,000 cycles as per jedec std. 22 method a117 and measured at ?40c, +25c, and +125c. typical endurance at 25c is 170,000 cycles. 12 retention lifetime equivalent at junction temperature (t j ) = 85c as per jedec std. 22 method a117. retention lifetime d erates with junction temperature. 13 voltage input levels only relevant if driving xtal input from a voltage source. if a crystal is connected directly, the inter nal crystal interface will determine the common mode voltage. 14 typical additional supply curre nt consumed during flash/ee memory program and erase cycles is 7ma . 15 total i dd for adc includes figures for pga32, input buffers, digital interface and the sigma delta modulator.
ADUCM360/aducm361 preliminary technical data rev. pr r page 10 of 21 ne reutn rar and auar ad table 2 : rms noise (v) vs. gain and output update rate (using an internal reference (1.2v) both adcs) update rate (hz) gain of 1 gain of 2 gain of 4 gain of 8 gain of 16 gain of 32 gain of 64 gain of 128 3.75 (chop on) adcxflt = 0x8d7c 1.05 0.45 0.23 0.135 0.072 0.064 0.055 0.052 30 (chop off) adcxflt = 0x007e 2.1 1.37 0.63 0.37 0.22 0.2 0.16 0.155 50 (chop off) adcxflt = 0x007d 3.7 1.6 0.83 0.47 0.29 0.24 0.21 0.2 100 (chop off) adcxflt = 0x004d 5.45 2.41 1.13 0.63 0.38 0.32 0.27 0.25 488 (chop off sinc4) adcxflt = 0x100f 10 4.7 2.2 1.3 0.79 0.67 0.58 0.57 976 (chop off sinc4) adcxflt = 0x1007 13.5 6.5 3.3 1.7 1.1 0.91 0.74 0.7 1953 (chop off sinc4) adcxflt = 0x1003 19.3 10 4.7 2.6 1.55 1.3 1.15 1.0 3906 (chop off sinc4) adcxflt = 0x1001 67.0 36 16.6 8.8 4.9 2.68 1.76 1.4 table 3 : typical output rms effective number of bits in normal mode (using an internal reference (1.2v), both adcs, peak - to - peak bits in parentheses) adc register status data update rate input voltage noise (mv) 1.0 v (pga = 1) 500 mv (pga = 2) 250 mv (pga = 4) 125 mv (pga = 8) 62.5 mv (pga = 16) 31.25 mv (pga = 32) 15.625 mv (pga = 64) 7.8125 mv (pga = 128) chop on sinc3 3.75 hz 21.1 (18.4p -p) 21.3 (18.6p -p) 21.3 (18.6p -p) 21.1 (18.4p -p) 21 (18.3p -p) 20.2 (17.4p -p) 19.4 (16.7p -p) 18.5 (15.7p -p) chop off sinc3 30 hz 20.1 (17.4p -p) 19.7 (17p -p) 19.8 (17.1p -p) 19.6 (16.9p -p) 19.4 (16.7p -p) 18.5 (15.8p -p) 17.8 (15.1p -p) 16.9 (14.2p -p) chop off sinc3 50 hz 19.3 (16.6p -p) 19.5 (16.8p -p) 19.5 (16.8p -p) 19.3 (16.6p -p) 19 (16.3p -p) 18.3 (15.5p -p) 17.4 (14.7p -p) 16.5 (13.8p -p) chop off sinc3 100 hz 18.7 (16p -p) 18.9 (16.2p -p) 19 (16.3p -p) 18.9 (16.2p -p) 18.6 (16.1p -p) 17.8 (15.1p -p) 17.1 (14.4p -p) 16.2 (13.5p -p) chop off sinc4 488 hz 17.9 (15.2p -p) 18 (15.2p -p) 18.1 (15.3p -p) 17.8 (15.1p -p) 17.5 (14.8p -p) 16.8 (14p -p) 16 (13.3p -p) 15 (12.3p -p) chop off sinc4 976 hz 17.4 (14.7p -p) 17.5 (14.8p -p) 17.5 (14.8p -p) 17.4 (14.7p -p) 17.1 (14.3p -p) 16.3 (13.6p -p) 15.6 (12.9p -p) 14.7 (12p -p) chop off sinc4 1953 hz 16.9 (14.2p -p) 16.9 (14.2p -p) 17 (14.3p -p) 16.8 (14p -p) 16.6 (13.8p -p) 15.8 (13.1p -p) 15 (13.1p -p) 14.2 (11.5p -p) chop off sinc4 3906 hz 15.1 (12.4p -p) 15 (12.3p -p) 15.1 (12.4p -p) 15.1 (12.4p -p) 14.9 (12.2p -p) 14.8 (12p -p) 14.4 (11.7p -p) 13.7 (11p -p)
preliminary technical data ADUCM360/aducm361 rev. pr r | page 11 of 21 table 4 : rms noise (v) vs. gain and output update rate (using an eternal reference (2.5v) bot adcs) update rate (hz) gain of 1 gain of 2 gain of 4 gain of 8 gain of 16 gain of 32 gain of 64 gain of 128 4.55 (chop on) adcxflt = 0x88fd 1.1 0.5 0.27 0.17 0.088 0.07 0.06 0.58 30 (chop off) adcxflt = 0x007e 3 1.4 0.85 0.44 0.27 0.22 0.19 0.17 50 (chop off) adcxflt = 0x007d 3.9 2.2 0.92 0.46 0.3 0.21 0.2 0.19 100 (chop off) adcxflt = 0x004f 5.2 2.8 1.25 0.63 0.38 0.32 0.28 0.26 488 (chop off sinc4) adcxflt = 0x100f 9.3 5.0 2.5 1.2 0.75 0.7 0.57 0.5 976 (chop off sinc4) adcxflt = 0x1007 12.5 7 3.5 1.75 1.2 0.83 0.77 0.75 1953 (chop off sinc4) adcxflt = 0x1003 20.0 10 5.7 2.6 1.71 1.3 1.24 1.1 3906 (chop off sinc4) adcxflt = 0x1001 140.0 70.0 35.0 17.2 8.9 4.8 2.65 1.88 table 5 : typical output rms effective number of bits in normal mode (using an eternal reference (2.5v) bot adcs peak to peak bits in parenteses) adc register status data update rate input voltage noise (mv) 1.0 v (pga = 1) 500 mv (pga = 2) 250 mv (pga = 4) 125 mv (pga = 8) 62.5 mv (pga = 16) 31.25 mv (pga = 32) 15.625 mv (pga = 64) 7.8125 mv (pga = 128) chop on sinc3 3.75 hz 22.1 (19.4p -p) 22.3 (19.5p -p) 22.1 (19.4p -p) 21.8 (19.1p -p) 21.8 (19.1p -p) 21.1 (18.4p -p) 20.3 (17.6p -p) 19.4 ( 16.6 p -p) chop off sinc3 30 hz 20.7 (18p -p) 20.7 (18p -p) 20.5 (17.7p -p) 20.5 (17.7p -p) 20.1 (17.4p -p) 19.4 (16.7p -p) 18.6 (15.9p -p) 17.8 (15.1p -p) chop off sinc3 50 hz 20.3 (17.6p -p) 20.1 (17.4p -p) 20.4 (17.7p -p) 20.4 (17.7p -p) 20 (17.3p -p) 19.5 (16.8p -p) 18.6 (15.9p -p) 17.6 (14.9p -p) chop off sinc3 100 hz 19.9 (17.2p -p) 19.8 (17p -p) 19.9 (17.2p -p) 19.9 (17.2p -p) 19.6 (16.9p -p) 18.9 (16.2p -p) 18.1 (15.4p -p) 17.2 (14.5p -p) chop off sinc4 488 hz 19 (16.3p -p) 18.9 (16.2p -p) 18.9 (16.2p -p) 19 (16.3p -p) 18.7 (15.9p -p) 17.8 (15p -p) 17.1 (14.3p -p) 16.3 (13.5p -p) chop off sinc4 976 hz 18.6 (15.9p -p) 18.4 (15.7p -p) 18.4 (15.7p -p) 18.4 (15.7p -p) 18 (15.3p -p) 17.5 (14.8p -p) 16.6 (13.9p -p) 15.7 (12.9p -p) chop off sinc4 1953 hz 17.9 (15.2p -p) 17.9 (15.2p -p) 17.7 (15p -p) 17.9 (15.2p -p) 17.5 (14.8p -p) 16.9 (14.2p -p) 15.9 (13.2p -p) 15.1 (12.4p -p) chop off sinc4 3906 hz 15.1 (12.4p -p) 15.1 (12.4p -p) 15.1 (12.4p -p) 15.1 (12.4p -p) 15.1 (12.4p -p) 15 (12.3p -p) 14.8 (12.1p -p) 14.3 (11.6p -p)
ADUCM360/aducm361 preliminary technical data rev. pr r page 12 of 21 tng dagra capacitive load for each of the i 2 c 1 - bus line, cb = 400pf maximum as per i 2 c - bus specifications. i 2 c timing is guaranteed by design and not production tested. table 6 . i 2 c timing in fast mode (400 khz) parameter description min ma unit t l serial clock (scl) low pulse width 1300 - ns t h scl high pulse width 600 - ns t shd start condition hold time 600 - ns t dsu data setup time 100 - ns t dhd data hold time 0 - ns t rsu setup time for repeated start 600 - ns t psu stop condition setup time 600 - ns t buf bus - free time between a stop condition and a start condition 1.3 - s t r rise time for both scl and serial data (sda) 20 + 0.1 cb 300 ns t f fall time for both scl and sda 20 + 0.1 cb 300 ns t sup pulse width of spike suppressed 0 50 ns table 7 . i 2 c timing in standard mode (100 khz) parameter description min ma unit t l scl low pulse width 4.7 - s t h scl high pulse width 4.0 - ns t shd start condition hold time 4.7 - s t dsu data setup time 250 - ns t dhd data hold time 0 - s t rsu setup time for repeated start 4.0 - s t psu stop condition setup time 4.0 - s t buf bus - free time between a stop condition and a start condition 4.7 - s t r rise time for both scl and sda - 1 s t f fall time for both scl and sda - 300 ns figure 2. i 2 c compatible interface timing 1 i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). 04955-054_edited sda (i / o ) t b u f msb l sb a c k msb 1 9 8 2 ? 7 1 sc l (i ) p s st o p c o n d i t i o n st a r t c o n d i t i o n s(r ) r epea t ed st a r t t s u p t r t f t f t r t h t l t s u p t d s u t d h d t r s u t d h d t d s u t s h d t p s u
preliminary technical data ADUCM360/aducm361 rev. pr r | page 13 of 21 spi timing diagrams table 8 . spi master mode timing parameter description min typ max unit t sl scl k low pulse width 1 (spidiv + 1) t uclk ns t sh scl k high pulse width 1 (spidiv + 1) t uclk ns t dav data output valid af ter scl k edge 0 35.5 ns t dosu data output setup before scl k edge 1 (spidiv + 1) t uclk ns t dsu da ta input setup time before scl k edge 58.7 ns t dhd data input hold time after scl k edge 16 ns t df data output fall time 12 35.5 ns t dr data output rise time 12 35.5 ns t sr scl k rise time 12 35.5 ns t sf scl k fall time 12 35.5 ns 1 t uclk = 62.5 ns . i t corresponds to the internal 16mhz clock before the clock divider. figure 3. spi master mode timing (phase mode = 1) 04955-055_edited sc lk (po l a r i t y = 0 ) sc lk (po l a r i t y = 1 ) mo si msb b i t s 6 t o 1 l sb mi so msb i n b i t s 6 t o 1 l sb i n t s h t s l t s r t s f t d r t d f t d a v t d s u t d h d
ADUCM360/aducm361 preliminary technical data rev. pr r page 14 of 21 iure . aster ode timin ae ode table 9 . spi slave mode timing parameter description min typ max unit t cs cs to scl k edge 38 ns t sl scl k low pulse width 1 (spidiv + 1) t uclk ns t sh scl k high pulse width 1 62.5 (spidiv + 1) t uclk ns t dav data output valid after scl k edge 49.1 ns t dsu da ta input setup time before scl k edge 20.2 ns t dhd data input hold time after scl k edge 10.1 ns t df data output fall time 12 35.5 ns t dr data output rise time 12 35.5 ns t sr scl k rise time 12 35.5 ns t sf scl k fall time 12 35.5 ns t docs data output valid after cs edge 25 ns t sfs cs high after scl k edge 0 ns 1 t uclk = 62.5 ns . i t corresponds to the internal 16mhz clock before the clock divider. 04955-056_edited sc lk (po l a r i t y = 0 ) sc lk (po l a r i t y = 1 ) t s h t s l t s r t s f mo si msb b i t s 6 t o 1 l sb mi so msb i n b i t s 6 t o 1 l sb i n t d r t d f t d a v t d o s u t d s u t d h d
preliminary technical data ADUCM360/aducm361 rev. pr r | page 15 of 21 figure 5. spi slave mode timing (phase mode = 1) figure 6. spi slave mode timing (phase mode = 0) 04955-057_edited sc lk (po l a r i t y = 0 ) c s sc lk (po l a r i t y = 1 ) t s h t s l t s r t s f t s f s mi so msb b i t s 6 t o 1 l sb mo si msb i n b i t s 6 t o 1 l sb i n t d h d t d s u t d a v t d r t d f t c s 04955-058_edited sc lk (po l a r i t y = 0 ) c s sc lk_ (po l a r i t y = 1 ) t s h t s l t s r t s f t s f s mi so mo si msb i n b i t s 6 t o 1 l sb i n t d h d t d s u msb b i t s 6 t o 1 l sb t d o c s t d a v t d r t d f t c s
ADUCM360/aducm361 preliminary technical data rev. pr r page 16 of 21 absolute maximum rat ings tale 10 parameter rating avdd /iovdd to g nd ?0.3 v to 3.96v digital input voltage to dgnd ?0.3 v to 3.96v digital output voltage to dgnd ?0.3 v to 3.96v v ref to agnd ?0.3 v to tbd analog inputs to agnd ?0.3 v to tbd operating temperature range C 40c to +125c storage temperature range C 65c to +150c junction temperature 150c esd (human body model) rating all pins 2kv ja thermal impedance 48- pin lfcsp _vq 27c/w peak solder reflow temperature snpb assemblies (10 sec to 30 sec) 240c pb - free assemblies (20 sec to 40 sec) 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specificati on is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
preliminary technical data ADUCM360/aducm361 rev. pr r | page 17 of 21 pin configuration and function descriptions figure 7. ADUCM360/aducm361 pinout table 11. pin function descriptions pin no. mnemonic description 1 reset reset. input pin, active low. an internal pull - up is provided. 2 p2.1/sda/uartdcd general - purpose input and general - purpose output p2.1/ i 2 c serial data pin/alternatively, this pin may be the uart data carrier detect pin. this is a multi function input/output pin. 3 p2.2/bm general - purpose input and general purpose output p2.2/ boot mode input select pin. when this pin is held low during any reset sequence, the part will enter uart download mode. this is a dual function input/output pin. 4 x tal0 external crystal oscillator output pin. optional 32 . 768khz source for real time clock. 5 x tal1 external crystal oscillator input pin. optional 32 . 768khz source for real time clock. 6 iovdd digital system supply pin. 7 dvdd_reg internal digital regulator supply output. this pin must be connected to ground via a 470nf capacitor. note: t his pin must be connected to pin 18, avdd_reg 8 ain0 adc analog input 0. this pin can be configured as a positive or negative inpu t to either adc in differential or single ended modes. 9 ain1 adc analog input 1. this pin can be configured as a positive or negative input to either adc in differential or single ended modes. 10 ain2 adc analog input 2. this pin can be configured as a positive or negative input to either adc in
ADUCM360/aducm361 preliminary technical data rev. pr r page 18 of 21 pin no. mnemonic description differential or single ended modes. 11 ain3 adc analog input 3. this pin can be configured as a positive or negative input to either adc in differential or single ended modes. 12 ain4/iexc adc analog input 4. this pin can be configured as a positive or negative input to either adc in differential or single ended modes. or, it may be configured as the output pin for either excitation current source 0 or 1. 13 gnd_sw sensor power switch to analog ground refer ence. 14 vref+ external reference positive input, an external reference can be applied between vref+ and vref -. 15 vref? external reference negative input, an external reference can be applied between vref+ and vref -. 16 agnd analog system ground reference pin . 17 avdd analog system supply pin. 18 avdd_reg internal analog regulator supply output. this pin must be connected to ground via a 470nf capacitor. note: t his pin must be connected to pin 7, dvdd_reg 19 dac dac voltage output 20 int_ref this pin must be connected to ground via a 470nf decoupling capacitor. 21 iref optional reference current resistor connection for the excitation current sources. reference current set by low drift external resistor (5ppm/c). 22 ain5/iexc multi - function pin: adc analog input 5. this pin can be configured as a positive or negative input to either adc in differential or single ended modes. alternatively, it may be configured as the output pin for either excitation current source 0 or 1. or, it may be configured as the output pin for either excitation current source 0 or 1. 23 ain6/iexc multi - function pin: adc analog input 6. this pin can be configured as a positive or negative input to either adc in differential o r single ended modes. or, it may be configured as the output pin for either excitation current source 0 or 1. 24 ain7/vbias0/iexc/ext_ref2in+ multi - function pin: adc analog input 7. this pin can be configured as a positive or negative input to either adc in differential or single ended modes. alternatively, this pin can be configured as an analog output pin to generate a bias voltage, vbias3 of av dd_reg /2. or, it may be configured as the output pin for either excitation current source 0 or 1. alternati vely, this pin can be configured as an external reference 2 positive input. 25 ain8/ext_ref2in - multi - function pin: adc analog input 8. this pin can be configured as a positive or negative input to either adc in differential or single ended modes. alternatively, this pin can be configured as an external reference 2 negative input. 26 ain9 adc analog input 9. this pin can be configured as a positive or negative input to either adc in differential or single ended modes. alternatively, this pin can be configured as the non - inverting input to the dac output buffer when the dac is configured for npn mode. 27 ain10 adc analog input 10. this pin can be configured as a positive or negative input to either adc in differential or single ended modes. 28 ain11/vbias1 multi - function pin: adc analog input 11. this pin can be configured as a positive o r negative input to either adc in differential or single ended modes. alternatively, this pin can be configured as an analog output pin to generate a bias voltage, vbias5 of avdd/2. 29 p0.0/miso1 general - purpose input and general - purpose output p0.0/spi1 master in C slave out pin. this is a dual function input/output pin. 30 p0.1/sclk1/scl/sin general - purpose input and general - purpose output p0.1/spi1 serial clock pin/i 2 c serial clock pin/ uart serial input. this is a multi function input/output pin. t his pin will be the data input for the uart downloader. 31 p0.2/mosi1/sda/sout general - purpose input and general - purpose output p0.2/ spi1 master out C slave in p in /i 2 c serial d ata pin / uart serial output. this is a multi function input/output pin. t his pin will be the data out put for the uart downloader. 32 p0.3/irq0/ cs1 general - purpose input and general - purpose output p0.3/ external interrupt request 0/ spi1 chip select pin (active low). this is a triple function input/output pin. 33 p0.4/rts/eclko general - purpose input and general - purpose output p0.4/ request - to - send si gnal in uart mode/ clock out (for test purposes) pin. this is a triple function input/output pin. 34 p0.5/cts/irq1 general - purpose input and general - purpose output p0.5/ clear - to - send signal in uart mode. / external interrupt request 1.
preliminary technical data ADUCM360/aducm361 rev. pr r | page 19 of 21 pin no. mnemonic description this is a dual function input/output pin. 35 p0.6/irq2/sin general - purpose input and general - purpose output p0.6/ external interrupt request 2/ uart serial input. this is a triple function input/output pin. 36 p0.7/por/sout general - purpose input and general - purpose out put p0.7 / power on reset active high bit/ uart serial output. this is a triple function input/output pin. 37 iovdd digital system supply pin. 38 p1.0/irq3/pwmsync/eclki general - purpose input and general purpose output p1.0/ external interrupt request 3/ pwm external sync input/external clock input pin. this is a quad function input/output pin. 39 p1.1/irq4/pwmtrip/dtr general - purpose input and general purpose output p1.1/ external interrupt request 4/ pwm external trip inp ut/uart data terminal ready pin. this is a multi function input/output pin. 40 p1.2/pwm0/ri general - purpose input and general - purpose output p1.2/pwm0 output/uart ring indicator pin. this is a triple function input/output pin. 41 p1.3/pwm1/dsr general - purpose input and general - purpose output p1.3/pwm1 output/uartdata set ready pin. this is a triple function input/output pin. 42 p1.4/pwm2/miso0 general - purpose input and general - purpose output p1.4/pwm2 output/ spi0 master in C slave out pin. this is a triple function input/output pin. 43 p1.5/irq5/pwm3/sclk0 general - purpose input and general - purpose output p1.5/ external interrupt request 5/ pwm3 output/ spi0 serial clock pin. this is a quad function input/output pin. 44 p1.6/irq6/pwm4/mosi 0 general - purpose input and general - purpose output p1.6/ external interrupt request 6/ pwm4 output/ spi0 master out, slave in pin. this is a quad function input/output pin. 45 p1.7/irq7/pwm5/ cs0 general - purpose input and general - purpose output p1.7/ external interrupt request 7/ pwm5 output/ spi0 chip select pin (active low). this is a quad function input/output pin. 46 p2.0/scl/uartclk general - purpose input and general purpose output p2.0/ i 2 c serial clock pin. alternatively, this pin may be an optional input clock pin for the uart block only. this is a triple function input/output pin. 47 swclk serial wire debug clock input pin. 48 swdio serial wire debug data input/output pin. ep **exposed paddle. the lfcsp_vq has an exposed paddle that must be connected to digital ground.
ADUCM360/aducm361 preliminary technical data rev. p r r page 20 of 21 typical performance characteristics figure 8 . common mode voltage (vcm) in volts vs input current in na, gain=4, adc input 250mv, avdd=3.6v, t=25c figure 9 . common mode voltage (vcm) in volts vs input current in na, gain=128, adc input 7.8125mv, avdd=3.6v, t=25c figure 10 . adc codes (decimal values) v die temperature 0 2000000 4000000 6000000 8000000 10000000 12000000 14000000 - 40 - 20 0 20 40 60 80 100 120 adc codes temp
preliminary technical data ADUCM360/aducm361 ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. pr09743 - 0 - 5/12(prr) . rev. pr r | page 21 of 21 outline dimensions (cp - 48- 4) figure 11 . 48 - lead lead frame chip scale package [lfcsp_vq] 7 mm 7 mm body, very thin quad dimensions shown in millimeters 112408-b for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. compliant to jedec standards mo-220- wkkd . 1 0.50 bsc bot t om view top view pin 1 indic a t or 7.00 bsc sq 48 13 24 25 36 37 12 exposed pa d pin 1 indic a t or 5.20 5.10 sq 5.00 0.45 0.40 0.35 sea ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.25 min 0.20 ref coplanarity 0.08 0.30 0.23 0.18

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